csaxs_bec.devices.epics.delay_generator_csaxs.ddg_1#
DDG1 delay generator
This module implements the DDG1 delay generator logic for the CSAXS beamline. The attached PDF trigger_scheme_ddg1_ddg2.pdf provides a more detailed overview of the trigger scheme. If the logic changes in the future, it is highly recommended to update the PDF accordingly.
The DDG1 is the main trigger delay generator for the CSAXS beamline. It will receive either a soft trigger from BEC (depending on the scan type) or a hardware trigger from a beamline device (e.g. the Galil stages). It is responsible for opening the shutter and sending a trigger to the Delay Generator CSAXS (DDG2), which in turn will send the trigger to the detectors. DDG1 will not be witout burst mode, but rather in standard mode creating delays for the channels ab, cd, ef, gh.
A brief summary of the DDG1 logic: DELAY PAIRS: - DelayPair ab is connected to the EXT/EN of DDG2. - DelayPair cd is connected to the SHUTTER. - DelayPair ef is connected to an OR gate together with the detector
PULSE train for the MCS card. The MCS card needs one extra pulse to forward points.
DELAY CHANNELS: - a = t0 + 2ms (2ms delay to allow the shutter to open) - b = a + 1us (short pulse) - c = t0 - d = a + exp_time * burst_count - e = d - f = e + 1us (short pulse to OR gate for MCS triggering)
Classes
Implementation of the DelayGenerator DDG1 for the cSAXS beamline. |