csaxs_bec.devices.epics.delay_generator_csaxs.ddg_2#
DDG2 delay generator
This module implements the DDG2 delay generator logic for the CSAXS beamline. Please check also the code for DDG1, aswell as the attached PDF trigger_scheme_ddg1_ddg2.pdf
The DDG2 is responsible for creating a burst of triggers for all relevant detectors. It will receive a be triggered from the DDG1 through the EXT/EN channel.
A brief summary of the DDG2 logic: DELAY PAIRS: - EXT/EN is connected to the DDG1 delay pair ab. - DelayPair ab is connected to a multiplexer, multiplexing the trigger to the detectors.
DELAY CHANNELS: - a = t0 - b = a + (exp_time - READOUT_TIMES)
Burst mode is enabled: - Burst count is set to the number of frames per trigger. - Burst delay is set to 0. - Burst period is set to the exposure time.
Classes
Implementation of the DelayGenerator DDG2 for the cSAXS beamline. |